1. Field of the Invention
This invention relates to electronic testing systems and, more particularly, to a formatter for combining timing signals with data from an algorithmic pattern generator in a memory test system.
2. Description of the Relevant Art
Memory test systems are known. Typically, such systems provide a prescribed electrical signal, e.g., a voltage waveform, to prescribed memory locations for a prescribed length of time. The test waveform ordinarily is generated by combining pattern data from an algorithmic pattern generator (APG) with timing signals from a timing unit. The test waveform then is transmitted to the test head (i.e.. drivers) connected to a device under test.
As memory size increases and access time decreases, the ability to generate high-speed test pattern waveforms becomes critical. For example, megabit static rams having access times of 10 to 20 nanoseconds are not uncommon, and the available access time must be used in order to test such memories in a timely and cost-effective manner. Unfortunately, signal propagation through the test system causes waveform skew, and this frequently renders the test waveform unusable by the device under test unless the waveform is properly deskewed. This is especially the case when generating test waveforms having such high speed timing noted above. When deskewing waveforms, each voltage transition (e.g., leading and trailing edges of a pulse) must be deskewed separately, and that is difficult, if not impossible, to do at high frequencies.